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19-1109; Rev 0; 7/96
N KIT MA ATION LE EVALU VAILAB A
UAL
500Msps, 8-Bit ADC with Track/Hold
_______________General Description
The MAX101A ECL-compatible, 500Msps, 8-bit analogto-digital converter (ADC) allows accurate digitizing of analog signals from DC to 250MHz (Nyquist frequency). Dual monolithic converters, driven by the track/hold (T/H), operate on opposite clock edges (time interleaved). Designed with Maxim's proprietary advanced bipolar processes, the MAX101A contains a high-performance T/H amplifier and two quantizers in an 84-pin ceramic flat pack. The innovative design of the internal T/H ensures an exceptionally wide 1.2GHz input bandwidth and aperture delay uncertainty of less than 2ps, resulting in a high 7.0 effective bits at the Nyquist frequency. Special comparator output design and decoding circuitry reduce out-of-sequence code errors. The probability of erroneous codes due to metastable states is reduced to less than 1 error per 1015 clock cycles. And, unlike other ADCs that can have errors resulting in false full-scale or zero-scale outputs, the MAX101A keeps the error magnitude to less than 1LSB. The analog input is designed for either differential or single-ended use with a 250mV range. Sense pins for the reference input allow full-scale calibration of the input range or facilitate ratiometric use. Phase adjustment is available to adjust the relative sampling of the converter halves for optimizing converter performance. Input clock phasing is also available for interleaving several MAX101As for higher effective sampling rates.
____________________________Features
o o o o o o o o o o 500Msps Conversion Rate 7.0 Effective Bits Typical at 250MHz 1.2GHz Analog Input Bandwidth Less than 1/2LSB INL 50 Differential or Single-Ended Inputs 250mV Input Signal Range Ratiometric Reference Inputs Dual Latched Output Data Paths Low Error Rate, Less than 10-15 Metastable States 84-Pin Ceramic Flat Pack
MAX101A
________________________Applications
High-Speed Digital Instrumentation High-Speed Signal Processing Medical Systems Radar/Signal Processing High-Energy Physics Communications
______________Ordering Information
PART MAX101ACFR* TEMP. RANGE 0C to +70C PIN-PACKAGE 84 Ceramic Flat Pack (with heatsink)
*Contact factory for 84-pin ceramic flat pack without heatsink.
_________________________________________________________Functional Diagram
VART VARTS VARBS VARB
MAX101A
8 AIN+ AINTRACK AND HOLD CLK CLK FLASH CONVERTER (8 -BIT) 8 FLASH CONVERTER (8 -BIT)
L A T C H E S
8 ADATA
STROBE
STROBE
B U F F E R
DCLK DCLK
TRK1
TRK1
PHADJ VBRT
VBRTS
VBRBS
VBRB
L A T C H E S
8 BDATA
________________________________________________________________ Maxim Integrated Products
1
For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
500Msps, 8-Bit ADC with Track/Hold MAX101A
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (Note 1) VCC ...........................................................................0V to +7V VEE .............................................................................-7V to 0V VCC - VEE .........................................................................+12V Analog Input Voltage .............................................................2V Reference Voltage (VART, VBRT)...........................-0.3V to +1.5V Reference Voltage (VARB, VBRB) ..........................-1.5V to +0.3V Clock Input Voltage (VIH, VIL) .....................................-2.3V to 0V DIV10 Input Voltage (VIH, VIL).......................................VEE to 0V Output Current, (IOUT(max)) TJ <100C .......................................................................14mA 100C < TJ <120C.........................................................12mA Operating Temperature Range...............................0C to +70C Operating Junction Temperature (Note 2)............0C to +120C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+250C
Note 1: The digital control inputs are diode protected. However, limited protection is provided on other pins. Permanent damage may occur on unconnected units under high-energy electrostatic fields. Keep unused units in supplied conductive carrier or shunt the terminals together. Note 2: Typical thermal resistance, junction-to-case RJC = 5C/W and thermal resistance, junction to ambient (MAX101ACFR) RJA =12C/W, if 200 lineal ft/min airflow is provided. See Package Information.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VEE = -5.2V, VCC = +5V, RL = 100 to -2V, VART, VBRT = 0.95V, VARB, VBRB = -0.95V, TA = +25C, unless otherwise noted. TMIN to TMAX = 0C to +70C.) (Note 3) PARAMETER ACCURACY Resolution Integral Nonlinearity (Note 4) Differential Nonlinearity DYNAMIC SPECIFICATIONS Effective Bits ENOB fCLK = 500MHz, VIN = 95% full scale (Note 5) fAIN = 10MHz fAIN = 125MHz fAIN = 250MHz 7.6 7.1 7.0 44.5 500 1.2 270 1 2 205 -290 -23 1.65 49 0.008 290 -205 23 2.35 51 Bits INL DNL AData, BData AData, BData, no missing codes TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX 8 0.50 0.75 0.75 0.85 Bits LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
6.7
Signal-to-Noise Ratio Maximum Conversion Rate Analog Input Bandwidth Aperture Width Aperture Delay Aperture Jitter ANALOG INPUT Input Voltage Range Input Offset Voltage Least Significant Bit Size Input Resistance Input Resistance Temperature Coefficient
SNR fCLK BW3dB tAW tAD tAJ
fAIN = 125MHz, fCLK = 500MHz, VIN = 95% full scale (Note 6) (Note 7) Figure 4 Figure 4 Figure 4 Full scale Zero scale AIN+, AIN-, TA = TMIN to TMAX TA = TMIN to TMAX AIN+, AIN-, to GND AIN+ to AIN-, Table 2, TA = TMIN to TMAX
dB Msps GHz ps ns ps
VIN VIO LSB RI
mV mV mV /C
2
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500Msps, 8-Bit ADC with Track/Hold
ELECTRICAL CHARACTERISTICS (continued)
(VEE = -5.2V, VCC = +5V, RL = 100 to -2V, VART, VBRT = 0.95V, VARB, VBRB = -0.95V, TA = +25C, unless otherwise noted. TMIN to TMAX = 0C to +70C.) (Note 3) PARAMETER REFERENCE INPUT Reference String Resistance Reference String Resistance Temperature Coefficient LOGIC INPUTS Digital Input Low Voltage Digital Input High Voltage Digital Input High Current Input Bias Current Clock Input Bias Current LOGIC OUTPUTS (Note 8) AData, BData Digital Output Low Voltage VOL DCLK, DCLK Digital Output High Voltage Digital Output Voltage POWER REQUIREMENTS Positive Supply Current Negative Supply Current Common-Mode Rejection Ratio Power-Supply Rejection Ratio IVCC IVEE CMRR PSRR VCC = 5.0V VEE = -5.2V VINCM = 0.5V VCC(nom) = 0.25V TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX TA = TMIN to TMAX VCC(nom) = 0.25V VEE(nom) = 0.25V -895 -935 35 40 40 415 855 910 -500 mA mA dB dB VOH AData, BData, DCLK, DCLK TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX -1.95 -1.95 -1.3 -1.4 -1.02 -1.10 275 -1.60 -1.50 -1.00 -0.9 -0.70 -0.60 445 V mV V VIL VIH IIH IB ICLK CLK, CLK, TA = TMIN to TMAX CLK, CLK, TA = TMIN to TMAX DIV10 = 0V, TA = TMIN to TMAX PHADJ = 0V, TA = TMIN to TMAX CLK, CLK = -0.8V (no termination), TA = TMIN to TMAX -1.1 1.1 -40 -50 3.1 40 50 -1.50 V V mA A A SYMBOL RREF VART to VARB CONDITIONS MIN 100 0.02 TYP MAX 190 UNITS /C
MAX101A
VOH - VOL DCLK, DCLK, TA = TMIN to TMAX
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500Msps, 8-Bit ADC with Track/Hold MAX101A
TIMING CHARACTERISTICS
(VEE = -5.2V, VCC = +5V, RL = 100 to -2V, VART, VBRT = 0.95V, VARB, VBRB = -0.95V, TA = +25C, unless otherwise noted.) PARAMETER Clock Pulse Width Low Clock Pulse Width High CLK to DCLK Propagation Delay DCLK to A/BData Propagation Delay Rise Time Fall Time Pipeline Delay (Latency) Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: SYMBOL tPWL tPWH tPD1 tPD2 tR tF tNPD CLK, CLK CLK, CLK DIV10 = 0, Figures 1 and 2 DIV10 = 0, Figures 1 and 2 20% to 80% 20% to 80% DCLK DATA DCLK DATA 15 CONDITIONS MIN 0.9 0.9 1.2 0.7 2.3 1.3 300 500 300 800 15 TYP MAX 2.5 2.5 3.4 1.8 UNITS ns ns ns ns ps ps Clock Cycles
Divide-by-1 mode See Divide-by-1 mode, Figures 2 and 3, Table 1 Figures 2, 3
All devices are 100% production tested at +25C and are guaranteed by design for TA = TMIN to TMAX as specified. Deviation from best-fit straight line. See Integral Nonlinearity section. See the Signal-to-Noise Ratio and Effective Bits section in the Detailed Description of Specifications. SNR calculated from effective bits performance using the following equation: SNR(dB) = 1.76 + 6.02 x effective bits. Clock pulse width minimum requirements tPWL and tPWH must be observed to achieve stated performance. Outputs terminated through 100 to -2.0V.
__________________________________________Typical Operating Characteristics
(VEE = -5.2V, VCC = +5V, RL = 100 to -2V, VART, VBRT = 0.95V, VARB, VBRB = -0.95V, TA = +25C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. OUTPUT CODE
MAX101 TOC1
DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE
MAX101 TOC2
0.75 0.50 0.25 0 -0.25 -0.50 -0.75 0 64 128 OUTPUT CODE 192
0.75 0.50 0.25 DNL (LSBs) 0 -0.25 -0.50 -0.75
INL (LSBs)
256
0
64
128 OUTPUT CODE
192
256
4
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500Msps, 8-Bit ADC with Track/Hold
____________________________Typical Operating Characteristics (continued)
(VEE = -5.2V, VCC = +5V, RL = 100 to -2V, VART, VBRT = 0.95V, VARB, VBRB = -0.95V, TA = +25C, unless otherwise noted.)
MAX101A
FFT PLOT (fAIN = 251.4462MHz)
MAX101 TOC3
FFT PLOT (fAIN = 10.4462MHz)
-10 -20 -30 -40 (dB) -50 -60 -70 -80 -90 -100 fCLK = 250MHz SER = -47.2dB NOISE FLOOR = -70.5dB SPURIOUS = -61.8dB
MAX101 TOC4
0 -10 -20 -30 -40 (dB) -50 -60 -70 -80 -90 -100 0 25 50
fCLK = 500MHz SER = -44.5dB NOISE FLOOR = -67.3dB SPURIOUS = -58.2dB
0
75 (MHz)
100
125
0
12.5
25
37.5 (MHz)
50
62.5
EFFECTIVE BITS vs. ANALOG INPUT FREQUENCY (fAIN) (fCLK = 500MHz, VIN = 95% FS)
MAX110 TOC5
EFFECTIVE BITS vs. CLOCK FREQUENCY (fCLK) (fAIN = 10.4462, VIN = 95% FS)
MAX110 TOC6
8
8
EFFECTIVE BITS
EFFECTIVE BITS
7
7
RECORD LENGTH = 512 6 0 50 100 150 200 fAIN (MHz) 250 300
6 0 100 200 300 400 fCLK (MHz) 500 600
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500Msps, 8-Bit ADC with Track/Hold MAX101A
____________________________Typical Operating Characteristics (continued)
(VEE = -5.2V, VCC = +5V, RL = 100 to -2V, VART, VBRT = 0.95V, VARB, VBRB = -0.95V, TA = +25C, unless otherwise noted.)
DATA CLOCK (DCLK) RISE TIME (360ps), DIV10 = OPEN
MAX101 TOC7
DATA CLOCK (DCLK) FALL TIME (315ps), DIV10 = OPEN
MAX101 TOC8
-550mV
-550mV
100mV/div
100mV/div
-1.55V -4.18ns
5.2ns
-1.55V -4.18ns
5.2ns
BDATA RISE TIME (504ps), DIV10 = OPEN
MAX101 TOC9
BDATA FALL TIME (827ps), DIV10 = OPEN
MAX101 TOC10
-825mV
-825mV
100mV/div
100mV/div
-1.825V -4.98ns
5.02ns
-1.825V -4.98ns
5.02ns
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500Msps, 8-Bit ADC with Track/Hold
______________________________________________________________Pin Description
PIN 1 2, 62 3, 61 4, 7, 15, 18, 24, 27, 30, 34, 37, 40, 46, 49, 57, 60, 64, 67, 68, 70, 71, 74, 77, 78, 79, 82, 84 5, 59 6, 58 8, 21, 43, 56, 81 9 10 11 12 13 14 16, 48, 63 29 31 33 32, 69, 80 35 36, 38, 39, 41, 42, 44, 45, 47 28, 26, 25, 23, 22, 20, 19, 17 NAME PAD CLK CLK Internal connection, leave open. Complementary Differential Clock Inputs. Can be driven from standard 10KH ECL with the following considerations: Internally, pins 2, 62 and 3, 61 are the ends of a 50 transmission line. Either end can be driven with the other end terminated with 50 to -2V. See Typical Operating Circuit. FUNCTION
MAX101A
GND
Power-Supply Ground
TRK1 Phasing inputs (normally left open). See Applications Information section. TRK1 VCC VBRB VBRBS TP4 TP3 VBRTS VBRT N.C. SUB DCLK DCLK VEE DIV10 A7-A0 Positive Power Supply, +5V 5% nominal "B" side negative reference voltage input (Note 9) "B" side negative reference voltage sense (Note 9) Internal connection, leave pin open. Internal connection, leave pin open. "B" side positive reference voltage sense (Note 9) "B" side positive reference voltage input (Note 9) No Connect--no internal connection to these pins. Circuit Substrate contact. This pin must be connected to VEE. Complementary Differential Clock Outputs. Used to synchronize following circuitry: Outputs A0-A7 are valid after DCLK's rising edge. B0-B7 output data are valid after DCLK's falling edge (see Figure 1 for output timing information). Negative Power Supply, -5.2V 5% nominal Divide by 10 mode. Leave open for normal operation. Selects test mode when grounded.
AData and BData Outputs. A0 and B0 are the LSBs, and A7 and B7 are the MSBs. AData and BData outputs conform to ECL logic swings and drive 100 transmission lines. Terminate with 100 to -2V (120 for Tj > +100C). See Figures 1-3.
B7-B0
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500Msps, 8-Bit ADC with Track/Hold MAX101A
_________________________________________________Pin Description (continued)
PIN 50 51 52 53 54 55 65 66 72, 73 75, 76 83 Note 9: NAME VART VARTS TP1 TP2 VARBS VARB TP5 TP6 AIN+ AINPHADJ FUNCTION "A" side positive reference voltage input (Note 9) "A" side positive reference voltage sense (Note 9) Internal connection, leave pin open. Internal connection, leave pin open. "A" side negative reference voltage sense (Note 9) "A" side negative reference voltage input (Note 9) Internal connection, leave pin open. Internal connection, leave pin open. Analog Inputs, internally terminated with 50 to ground. Full-scale linear input range is approximately 250mV. Drive AIN+ and AIN- differentially for best high-frequency performance. Phase adjustment for T/H. Normally connected to ground. A phase adjustment of approximately 18ps can be made by varying this pin's bias point to optimize interleaving between sides A and B (Note 10).
VART, VARB, VBRT, and VBRB should be adjusted separately from a well bypassed reference circuit to ensure proper amplitude and offset matching. The sense connections to each of these terminals allows precision setting of the reference voltage. The reference ladder is similar for both converter halves (check electrical section for values). Any noise on these terminals will severely reduce overall performance. Note 10: Good results are obtained by connecting the PHADJ input to ground. Improve performance by applying a voltage between 1.25V to this input. The time that the "A" T/H bridge samples relative to the time that the "B" T/H bridge samples can be varied through a 18ps range.
CLK CLK tPWH DCLK DCLK tPD1 ADATA tPWL
BDATA tPD2 tPD2
Figure 1. Output Timing, Normal Mode (DIV10 = OPEN)
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500Msps, 8-Bit ADC with Track/Hold MAX101A
CLK N-1 N N+1 N+2 +14 +15 +16 +17
0 DCLK
1
7
8
ADATA
N-1
N+1
N+3
BDATA tPD2 tPD2
N-2
N
N+2
NOTE: DATA ARBITRARY ON START-UP FOR SIDE A OR B, SEE INPUT CLOCK PHASING SECTION.
Figure 2. Output Timing, Clock to Data, Normal Mode (DIV10 = OPEN)
CLK
N
N+1
N+2
N+3
+15
+16
+17
DCLK
ADATA
N
BDATA
N+5
NOTE: DATA ARBITRARY ON START-UP FOR SIDE A OR B, SEE INPUT CLOCK PHASING SECTION.
Figure 3. Output Timing, Test Mode (DIV10 = GND)
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500Msps, 8-Bit ADC with Track/Hold MAX101A
______Definitions of Specifications
Signal-to Noise Ratio and Effective Bits
Signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other analog-to-digital (A/D) output signals. The theoretical minimum A/D noise is caused by quantization error and is a direct result of the ADC's resolution: SNR = (6.02N + 1.76)dB, where N is the number of effective bits of resolution. Therefore, a perfect 8-bit ADC can do no better than 50dB. The FFT plots in the Typical Operating Characteristics show the output level in various spectral bands. Effective bits is calculated from a digital record taken from the ADC under test. The quantization error of the ideal converter equals the total error of the device. In addition to ideal quantization error, other sources of error include all DC and AC nonlinearities, clock and aperture jitter, missing output codes, and noise. Noise on references and supplies also degrades effective bits performance. The ADC's input is sine-wave filtered with an anti-aliasing filter to remove any harmonic content. The digital record taken from this signal is compared against a mathematically generated sine wave. DC offsets, phase, and amplitudes of the mathematical model are adjusted until a best-fit sine wave is found. After subtracting this sine wave from the digital record, the residual error remains. The RMS value of the error is applied in the following equation to yield the ADC's effective bits. measured RMS error Effective bits = N - log2 ------------------ideal RMS error where N is the resolution of the converter. In this case, N = 8. The worst-case error for any device will be at the converter's maximum clock rate with the analog input near the Nyquist rate (one-half the input clock rate).
CLK CLK tAW ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
TRACK T/H
HOLD APERTURE DELAY (tAD) APERTURE WIDTH (tAW) APERTURE JITTER (tAJ)
TRACK
Figure 4. T/H Aperture Timing
typical converters can be incorrect, including false full- or zero-scale output. The MAX101A's unique design reduces the magnitude of this type of error to 1LSB, and reduces the probability of the error occurring to less than one in every 1015 clock cycles. If the MAX101A were operated at 500MHz, 24 hours a day, this would translate to less than one metastable state error every 46 days.
Integral Nonlinearity
Integral nonlinearity is the deviation of the transfer function from a reference line measured in fractions of 1LSB using a "best straight line" determined by a least square curve fit.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the measured LSB step and an ideal LSB step size between adjacent code transitions. DNL is expressed in LSBs and is calculated using the following equation: [VMEAS - (VMEAS - 1)] - LSB DNL(LSB) = ----------------------------LSB where VMEAS - 1 is the measured value of the previous code. A DNL specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.
Aperture Width and Jitter
Aperture width is the time the T/H circuit takes to disconnect the hold capacitor from the input circuit (i.e., to turn off the sampling bridge and put the T/H in hold mode). Aperture jitter is the sample-to-sample variation in aperture delay (Figure 4).
Error Rates
Errors resulting from metastable states may occur when the analog input voltage, at the time the sample is taken, falls close to the decision point for any one of the input comparators. The resulting output code for many
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500Msps, 8-Bit ADC with Track/Hold
_______________Detailed Description
Converter Operation
The parallel or "flash" architecture used by the MAX101A provides the fastest multibit conversion of all common integrated ADC designs. The basic element of a flash, as with all other ADC architectures, is the comparator, which has a positive input, a negative input, and an output. If the voltage at the positive input is higher than the negative input (connected to a reference), the output will be high. If the positive input voltage is lower than the reference, the output will be low. A typical n-bit flash consists of 2n - 1 comparators with negative inputs evenly spaced at 1LSB increments from the bottom to the top of the reference ladder. For n = 8, there are 255 comparators. For any input voltage, all the comparators with negative inputs connected to the reference ladder below the input voltage will have outputs of 1 and all comparators with negative inputs above the input voltage will have outputs of 0. Decode logic is provided to convert this information into a parallel n-bit digital word (the output) corresponding to the number of LSBs (minus 1) that the input voltage is above the bottom of the ladder. The comparators contain latch circuitry and are clocked. This allows the comparators to function as described previously when, for example, clock is low. When clock goes high (samples) the comparator will latch and hold its state until the clock goes low again. The MAX101A uses a monolithic, dual-interleaved parallel quantizer chip with two separate 8-bit converters. These converters deliver results to the A and B output latches on alternate negative edges of the input clock.
MAX101A
Table 1. Output Mode Control
DIV10 DCLK* (MHz) 250 MODE Normal Divide by 2 Test Divide by 10 DESCRIPTION AData and BData valid on opposite DCLK edges (AData on rise, BData on fall). AData and BData valid on opposite DCLK edges (AData on rise, BData on fall). Data sampled at input CLK rate but 4 out of every 5 samples discarded.
OPEN
GND
50
* Input clocks (CLK, CLK) = 500MHz for all above combinations. In all modes, the output clock DCLK will be a 50% duty-cycle signal.
Data Flow
The MAX101A's internal T/H amplifier samples the analog input voltage for the ADC to convert. The T/H is split into two sections that operate on alternate negative clock edges. The input clock, CLK, is conditioned by the T/H and fed to the A/D section. The output clock, DCLK, used for output data timing, will be divided by 2 or 10 from the input clock (Table 1). This results in an output data rate of 250Mbps on each output port in normal mode and 50Mbps in test mode. The differential inputs, AIN+ and AIN-, are tracked continuously between data samples. When a negative strobe edge is sensed, one-half of the T/H goes into hold mode (Figure 4). When the strobe is low, the just-acquired sample is presented to the ADC's input comparators. Internal processing of the sampled data takes an additional 15 clock cycles before it is available at the outputs, AData and BData. See Figures 1-3 for timing.
Track/Hold
As with all ADCs, if the input waveform is changing rapidly during the conversion, the effective bits and SNR will decrease. The MAX101A has an internal track/hold (T/H) that increases attainable effective-bits performance and allows more accurate capture of analog data at high conversion rates. The internal T/H circuit provides two important circuit functions for the MAX101A: 1) Its nominal voltage gain of 4 reduces the input driving signal to 250mV differential (assuming a 0.95V reference). 2) It provides a differential 50 input that allows easy interface to the MAX101A.
__________Applications Information
Analog Input Ranges
Although the normal operating range is 250mV, the MAX101A can be operated with up to 500mV on each input with respect to ground. This extended input level includes the analog signal and any DC common-mode voltage. To obtain full-scale digital output with differential input drive, a nominal +250mV must be applied between AIN+ and AIN-. That is, AIN+ = +125mV and AIN- = -125mV (with no DC offset). Mid-scale digital output code occurs when there is no voltage difference across the analog inputs. Zero-scale digital output code, with differential -250mV drive, occurs when AIN+ = -125mV and AIN- = +125mV. Table 2 shows how the output of the converter stays at all ones (full scale) when over-ranged or all zeros (zero scale) when underranged.
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500Msps, 8-Bit ADC with Track/Hold MAX101A
Table 2. Input Voltage Range
INPUT AIN+ (mV) +125 Differential 0 -125 +250 Single Ended 0 -250 AIN(mV) -125 0 +125 0 0 0 OUTPUT CODE 11111111 10000000 MSB to LSB full scale mid scale
PARASITIC RESISTANCE POSITIVE REFERENCE
VART
0 0 0 0 0 0 0 0 zero scale 11111111 10000000 full scale mid scale VARTS
0 0 0 0 0 0 0 0 zero scale
R
* An offset VIO, as specified in the DC electrical parameters, will be present at the input. Compensate for this offset by adjusting the reference voltage. Offsets may be different between side A and side B.
For single-ended operation: 1) Apply a DC offset to one of the analog inputs, or leave one input open. (Both AIN+ and AIN- are terminated internally with 50 to analog ground.) 2) Drive the other input with a 250mV + offset to obtain either full- or zero-scale digital output. If a DC common-mode offset is used, the total voltage swing allowed is 500mV (analog signal plus offset with respect to ground).
TO COMPARATORS R
R
Reference
The ADC's reference resistor is a Kelvin-sensed, resistor string that sets the ADC's LSB size and dynamic operating range. Normally, the top and bottom of this string are driven with an external buffer amplifier. It will need to supply approximately 19mA due to the 100 minimum resistor string impedance. A 0.95V reference voltage is normally applied to inputs VART, VBRT, VARB, and VBRB. The reference inputs VARTS, VARBS, VBRTS, and VBRBS allow Kelvin sensing of the applied voltages to increase precision. An RC network at the ADC's reference terminals is needed for best performance. This network consists of a 33 resistor connected in series with the buffer output that drives the reference. A 0.47F capacitor must be connected near the resistor at the buffer's output (see Typical Operating Circuit). This resistor and capacitor combination should be located within 0.5 inches of the MAX101A package. Any noise on these pins will directly affect the code uncertainty and degrade the ADC's effective-bits performance.
R
R
VARBS
PARASITIC RESISTANCE
VARB
NEGATIVE REFERENCE
Figure 5. Reference Ladder
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500Msps, 8-Bit ADC with Track/Hold
CLK and DCLK
All input and output clock signals are differential. The input clocks, CLK and CLK, are the primary timing signals for the MAX101A. CLK (pins 2, 62) and CLK (pins 3, 61) are fed to the internal circuitry through an internal 50 transmission line. One set of CLK, CLK inputs should be driven and the other pair terminated by 50 to -2V. Either set of inputs can be used as the driven inputs (input lines are balanced) for easy circuit connection. A minimum pulse width (tPWL) is required for CLK and CLK (Figures 1-3). For best performance and consistent results, use a lowphase-jitter clock source for CLK and CLK. Phase jitter larger than 2ps from the input clock source reduces the converter's effective bits performance and causes inconsistent results. The clock supplied to the MAX101A is internally divided by two, reshaped, and buffered. This divided clock becomes the internal signal used as strobes for the converters. DCLK and DCLK are output clock signals derived from the input clocks and are used for external timing of the AData and BData outputs. (AData is valid after the rising edge of DCLK, and BData is valid after the falling edge.) They are fixed at one-half the rate of the input clocks in normal mode (Table 1). The MAX101A is characterized to work with 500MHz maximum input clock frequencies. See Typical Operating Circuit.
Layout, Grounding, and Power Supplies
A +5V 5% supply as well as a -5.2V 5% supply is needed for proper operation. Bypass the VEE and VCC supply pins to GND with high-quality 0.1F and 0.001F ceramic capacitors located as close to the package as possible. Connect all ground pins to a ground plane to optimize noise immunity and device accuracy. Turn on the fan before connecting the power supplies. See Package Information for the required airflow.
MAX101A
Phase Adjust
This control pin affects the point in time that one-half of the converter samples the input signal relative to the other half. PHADJ is normally connected to ground (0V), but can be adjusted over a 1.25V range that typically provides a 18ps adjustment between the "A" side T/H bridge strobe and the "B" side T/H bridge strobe.
Interleaving (Input Clock Phasing)
To interleave two MAX101As it is necessary to know on which positive edge of the input clock data will change. At power-up, the clock edge from which AData and BData are synchronized is undetermined. The converter can work from a specific input clock edge, as described in the following paragraph. TRK1 and TRK1 are differential inputs that are used in addition to the normal input clock (CLK) to set data phasing. A signal at one-half the input clock rate with the proper setup and hold times (setup and hold typically 300ps) is applied to these inputs. Choose AData by applying a logic "1" to TRK1 ("0" to TRK1) before CLK's negative transition. Choose BData by applying a logic "0" to TRK1 before CLK's negative edge ("1" to TRK1). Voltages at the TRK1 input between 50mV are interpreted as logic "1" and voltages between -350mV and -500mV are interpreted as logic "0".
Output Mode Control (DIV10)
When DIV10 is grounded, it enables the test mode, where the input incoming clock is divided by ten. This reduces the output data and clock rates by a factor of 5, allowing the output clock duty cycle to remain at 50%. The clock to output phasing remains the same and four out of every five sampled input values are discarded. When left open, this input (DIV10) is pulled low by internal circuitry and the converter functions in its normal mode.
______________________________________________________________________________________
13
500Msps, 8-Bit ADC with Track/Hold MAX101A
____________________________________________________________Pin Configuration
TOP VIEW
PHADJ
GND
GND
GND
GND
AIN+
GND
GND
AIN+
GND
GND
GND
GND
AIN-
AIN-
VCC
84
83
82
81
80
VEE
79
78
77
76
75
74
73
72
71
70
69
V EE
68
67
66
65
PAD CLK CLK GND TRK1 TRK1 GND VCC VBRB VBRBS TP4 TP3 VBRTS VBRT GND N.C. B0 GND B1 B2 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 24 25 26 27 28 29 30 31 32 33 35 36 37 38 40 41 22 34 23 39 42
64 63 N.C. 62 CLK 61 CLK 60 GND 59 58 57 56 55 TRK1 TRK1 GND VCC VARB VARBS 54 53 TP2 52 TP1 51 VARTS 50 VART 49 48 47 46 45 44 43 GND N.C. A0 GND A1 A2 VCC A3
MAX101A
GND
GND
DCLK
A6
SUB
A7
GND
GND
Ceramic Flat Pack
14
______________________________________________________________________________________
DIV10
GND
DCLK
GND
VEE
A5
B3
B4
B5
B6
B7
A4
GND
TP6
TP5
500Msps, 8-Bit ADC with Track/Hold MAX101A
___________________________________________________Typical Operating Circuit
+5V 0.01F 1
+VS VOUT GND
+5V 2.5V
0.1F 0.001F MC100E151
2 0.01F
MX580LH
3
2k 500 1.2k 0.01F
1/2 MAX412 20
0.47F 50 20k
8, 21, 43, 56, 81 33 50 VART VCC
D >
Q Q
CMPSH-3 51 50 54 VARTS VARBS ADATA 8 D > Q Q
2k 20k 500 1.2k WATKINS-JOHNSON SMRA 89-1 (2x)
0.01F
1/2 MAX412 20 33
0.47F 10k
55
VARB
CMPSH-3
MAX101A
72, 73 AIN+ DCLK DCLK 75, 76 AIN33 31
2k 500 1.2k 0.01F
1/2 MAX412 20
0.47F 50 20k
33
MC100E151 14 VBRT D > VBRTS VBRBS BDATA 8 D > 9 VBRB +1.25V Q Q Q Q
CMPSH-3 13 50 10
2k 20k 500 1.2k
0.01F
1/2 MAX412 20 33
0.47F 10k CMPSH-3
62 50 -2V MC100E116 50 -2V 3 2 61 CLK GND 4, 7, 15, 18, 24, 27, 30, 34, 37, 40, 46, 49, 57, 60, 64, 67, 68, 70, 71, 74, 77, 78, 79, 82, 84 SUB 29 CLK
PHADJ
83
PHASE
-1.25V
VEE 32, 69, 80 0.001F -5.2V 0.1F
______________________________________________________________________________________
15
500Msps, 8-Bit ADC with Track/Hold MAX101A
________________________________________________________Package Information
PIN FIN HEATSINK FORCED CONVECTION PARAMETERS
21 19 JA (C/W) 17 15 0 Angle* 13 11 45 Angle* 9 7 0 100 200 300 400 500 VELOCITY (ft /min) *DIRECTION OF AIRFLOW ACROSS HEATSINK
MAX100-insertB
23
E1 E E2 e
DIM S 0.060.005(7x)
D1 D D2 D3
PIN #1 C b A2 A1
0.075.020(6x) EQUAL SPACES
MILLIMETERS MIN MAX A 17.272 18.288 A1 1.041 1.270 A2 3.048 3.302 b 0.406 0.508 C 0.228 0.279 D 29.184 29.794 D1 44.196 44.704 D2 25.298 25.502 D3 28.448 28.829 1.270 BSC e E 29.184 29.794 E1 44.196 44.704 E2 25.298 25.502 E3 28.194 28.702 S 1.930 2.184
INCHES MIN MAX 0.680 0.720 0.041 0.050 0.120 0.130 0.016 0.020 0.009 0.011 1.149 1.173 1.740 1.760 0.996 1.004 1.120 1.135 0.050 BSC 1.149 1.173 1.740 1.760 0.996 1.004 1.110 1.130 0.076 0.086
A 5-6 E3
84-PIN CERAMIC FLAT PACK WITH HEAT SINK
0.060.005
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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